Technology such as an FPGA (Field Programmable Gate Array) or a DRP (Dynamically Reconfigurable Processor) has been proposed as reconfigurable hardware. Related technology is disclosed in Japanese Patent Publication Number 3987782, Japanese Patent Publication Number 3987783, and Unexamined Japanese Patent Application KOKAI Publication No. 2006-202330.
A design method using behavioral synthesis tools is effective in the design of electronic circuits implemented using reconfigurable hardware. The behavioral synthesis tools are tools that output RTL (Register Transfer Level) descriptions by subjecting behavioral level descriptions including information required for hardware implementation such as the bit width etc. of input ports and variables to behavioral synthesis.
Typically, a technique referred to as “static compiling” where optimization is carried out using only information acquired from the behavioral level description can be used in the field of behavioral synthesis.